This invention relates generally to semiconductor technology and more particularly to metal-ferroelectric-insulator semiconductor (MFIS) transistor structures, and methods of fabrication. An MFIS transistor is similar to an MFOS transistor, but is not limited to structures that use oxide as the insulator material.
Previously, single transistor ferroelectric memory transistors have utilized a ferroelectric electrode stack, comprising a ferroelectric gate with a top electrode. The device would be formed by depositing a ferroelectric material, followed by an overlying metal layer. The layers would then be plasma etched. Plasma etching degrades the ferroelectric properties of the ferroelectric gate, thereby reducing the reliability of the memory transistor. The ferroelectric material also needed to be passivated to prevent contamination from hydrogen. Passivation was also used to reduce unwanted interactions between the ferroelectric material and underlying oxide.
A ferroelectric transistor structure is provided comprising a ferroelectric gate overlying a semiconductor substrate. The ferroelectric gate has a bottom with a gate dielectric interposed between the bottom and the semiconductor substrate. The ferroelectric gate also has sides with adjacent passivation sidewalls, and a top covered with a top electrode. The top electrode, the passivation sidewalls and the gate dielectric serve to encapsulate the ferroelectric gate, thereby reducing, or eliminating, contamination due to oxygen, hydrogen or other contaminants.
A method of forming the ferroelectric gate structure of the present invention is also provided. A gate insulation material is formed over the substrate. A sacrificial gate structure is formed overlying the gate insulation material and removed to produce an open gate region. A passivation insulator is deposited over the substrate, including the open gate region. The passivation insulator is anisotropic plasma etched to form passivation sidewalls. A ferroelectric material is deposited over the substrate including the open gate region and then polished using CMP. A top electrode is then formed over the remaining ferroelectric material. The combination of the top electrode, the passivation sidewalls and the gate insulation serve to encapsulate and protected the ferroelectric material.
The gate insulator is preferably ZrO2, zirconium silicate, Zrxe2x80x94Alxe2x80x94Sixe2x80x94O, HfO2, hafnium silicate, Hfxe2x80x94Alxe2x80x94O, Laxe2x80x94Alxe2x80x94O, lanthanum oxide Ta2O5, or other suitable high-k material. However, the gate insulator may also be silicon nitride, nitrogen implanted silicon dioxide, or silicon oxynitride.
The passivation sidewalls are preferably TiO2, Al2O3, TiAlOx, or Si3N4 
The ferroelectric material is preferably PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO, YMnO3, or other suitable material.
The top electrode is preferably iridium, platinum, ruthenium, iridium oxide, platinum oxide, ruthenium oxide, or other suitable material.